Class Summary 
addsubX 
Generic width addersubtractor. 
addX 
Generic width adder. 
and2_dp 
This class implements and asynchronous 2input and gate. 
and2_dp_g 
This class implements and asynchronous 2input and gate. 
and3_dp 
This class implements and asynchronous 3input and gate. 
and3_dp_g 
This class implements and asynchronous 3input and gate. 
and4_dp 
This class implements and asynchronous 4input and gate. 
and5_dp 
This class implements and asynchronous 5input and gate. 
and6_dp 
This class implements and asynchronous 6input and gate. 
and7_dp 
This class implements and asynchronous 7input and gate. 
and8_dp 
This class implements and asynchronous 8input and gate. 
and9_dp 
This class implements and asynchronous 9input and gate. 
andX 
This class implements an AND gate with arbitrary number of inputs. 
buf 
Buffer. 
bufX 
This cell buffers each input wire. 
Constant 
This class is a structural cell which drives a constant value
on to its output wire. 
CSRCCL 

CSRCClockDriver 

CSRCFD 

CSRCTechMapper 

CSRCWire 

dff_dp 
The dff_dp is a simple Dflipflop. 
dff_dpX 
This instantiates a generic width dff_dp. 
dffe_dp 
The dffe_dp is a Dflipflop with a clock enable. 
dffe_dpX 
This instantiates a generic width dffe_dp. 
dffr_dp 
The dffr_dp is a Dflipflop with a synchronous reset. 
dffr_dpX 
This instantiates a generic width dffs_dp. 
dffre_dp 
The dffre_dp is a Dflipflop with a synchronous reset
and a clock enable. 
dffre_dpX 
This instantiates a generic width dffre_dp. 
dffs_dp 
The dffs_dp is a Dflipflop with a synchronous set. 
dffs_dpX 
This instantiates a generic width dffr_dp. 
dffse_dp 
The dffse_dp is a Dflipflop with a synchronous set
and a clock enable. 
dffse_dpX 
This instantiates a generic width dffse_dp. 
DL_ONE 
Returns a logic one. 
DL_ZERO 
Returns a logic zero. 
gndX 
This instantiates a generic width vcc. 
IB 
This is an input buffer. 
IBX 
Generic width output buffer. 
maj3 
3input majority gate. 
mux_dpX 
Generic width 21 Mux. 
mux3_dp 
21 Mux. 
nand2_dp 
This class implements and asynchronous 2input nand gate. 
nand2_dp_g 
This class implements and asynchronous 2input nand gate. 
nand3_dp 
This class implements and asynchronous 3input nand gate. 
nand3_dp_g 
This class implements and asynchronous 3input nand gate. 
nand4_dp 
This class implements and asynchronous 4input nand gate. 
nand5_dp 
This class implements and asynchronous 5input nand gate. 
nand6_dp 
This class implements and asynchronous 6input nand gate. 
nand7_dp 
This class implements and asynchronous 7input nand gate. 
nand8_dp 
This class implements and asynchronous 8input nand gate. 
nand9_dp 
This class implements and asynchronous 9input nand gate. 
nandX 
This class implements an NAND gate with arbitrary number of inputs. 
nor2_dp 
This class implements and asynchronous 2input nor gate. 
nor2_dp_g 
This class implements and asynchronous 2input nor gate. 
nor3_dp 
This class implements and asynchronous 3input nor gate. 
nor3_dp_g 
This class implements and asynchronous 3input nor gate. 
nor4_dp 
This class implements and asynchronous 4input nor gate. 
nor5_dp 
This class implements and asynchronous 5input nor gate. 
nor6_dp 
This class implements and asynchronous 6input nor gate. 
nor7_dp 
This class implements and asynchronous 7input nor gate. 
nor8_dp 
This class implements and asynchronous 8input nor gate. 
nor9_dp 
This class implements and asynchronous 9input nor gate. 
norX 
This class implements an NOR gate with arbitrary number of inputs. 
not_dp 
Inverter. 
notX 
This cell inverts each input wire. 
OB 
This is an output buffer. 
OBT 
This is an output buffer with a (high?) asserted output enable. 
OBTX 
Generic width output buffer. 
OBX 
Generic width output buffer. 
or2_dp 
This class implements and asynchronous 2input or gate. 
or2_dp_g 
This class implements and asynchronous 2input or gate. 
or3_dp 
This class implements and asynchronous 3input or gate. 
or3_dp_g 
This class implements and asynchronous 3input or gate. 
or4_dp 
This class implements and asynchronous 4input or gate. 
or5_dp 
This class implements and asynchronous 5input or gate. 
or6_dp 
This class implements and asynchronous 6input or gate. 
or7_dp 
This class implements and asynchronous 7input or gate. 
or8_dp 
This class implements and asynchronous 8input or gate. 
or9_dp 
This class implements and asynchronous 9input or gate. 
orX 
This class implements an OR gate with arbitrary number of inputs. 
Shifter 
This shifter was taken straight from the Xilinx directory. 
subX 
Generic width subtractor. 
TESTCSRCLibrary 
This class is the selftest controller for the CSRC library. 
vccX 
This instantiates a generic width vcc. 
xnor2_dp 
This class implements and asynchronous 2input xnor gate. 
xnor2_dp_g 
This class implements and asynchronous 2input xnor gate. 
xnor3_dp 
This class implements and asynchronous 3input xnor gate. 
xnor3_dp_g 
This class implements and asynchronous 3input xnor gate. 
xnor4_dp 
This class implements and asynchronous 4input xnor gate. 
xnor5_dp 
This class implements and asynchronous 5input xnor gate. 
xnor6_dp 
This class implements and asynchronous 6input xnor gate. 
xnor7_dp 
This class implements and asynchronous 7input xnor gate. 
xnor8_dp 
This class implements and asynchronous 8input xnor gate. 
xnor9_dp 
This class implements and asynchronous 9input xnor gate. 
xnorX 
This class implements an XNOR gate with arbitrary number of inputs. 
xor2_dp 
This class implements and asynchronous 2input xor gate. 
xor2_dp_g 
This class implements and asynchronous 2input xor gate. 
xor3_dp 
This class implements and asynchronous 3input xor gate. 
xor3_dp_g 
This class implements and asynchronous 3input xor gate. 
xor4_dp 
This class implements and asynchronous 4input xor gate. 
xor5_dp 
This class implements and asynchronous 5input xor gate. 
xor6_dp 
This class implements and asynchronous 6input xor gate. 
xor7_dp 
This class implements and asynchronous 7input xor gate. 
xor8_dp 
This class implements and asynchronous 8input xor gate. 
xor9_dp 
This class implements and asynchronous 9input xor gate. 
xorX 
This class implements an XOR gate with arbitrary number of inputs. 