byucc.jhdl.Xilinx.XC4000
Classes 
and2
and2_g
and2b1
and2b2
and3
and3_g
and3b1
and3b2
and3b3
and4
and4_g
and4b1
and4b2
and4b3
and4b4
and5
and6
and7
and8
and9
andX
bscan
buf
buf_g
bufe
buffclk
bufg
bufg_ann
bufge
bufge_ann
bufgls
bufgls_ann
bufgp
bufgp_ann
bufgs
bufgs_ann
buft
buft_g
cy4
cy4_mode
d3_8e
fd
fd_1
fdc
fdc_1
fdc_1_g
fdce
fdce_1
fdce_g
fde
fde_1
fdp
fdp_1
fdp_1_g
fdpe
fdpe_1
fdpe_g
fdr
fdr_1
fdr_1_g
fdre
fdre_1
fdre_1_g
fdrs
fdrs_1
fdrs_1_g
fdrs_g
fdrse
fdrse_1
fdrse_1_g
fdrse_g
fds
fds_1
fds_1_g
fdse
fdse_1
fdse_1_g
fmap
fmap_g
gnd
hmap
ibuf
ibuf_ann
ibuf_g
ifd
ifd_1
ifdi
ifdi_1
ifdx
ifdxi
ildx_1
ildxi_1
ilffx
ilffxi
ilflx_1
ilflxi_1
inv
inv_g
iopad
ipad
ipad_sim
ldce
ldce_1
ldpe_1
m2_1
m2_1_g
md0
md1
md2
nand2
nand2_g
nand2b1
nand2b2
nand3
nand3_g
nand3b1
nand3b2
nand3b3
nand4
nand4_g
nand4b1
nand4b2
nand4b3
nand4b4
nand5
nand6
nand7
nand8
nand9
nandX
nor2
nor2_g
nor2b1
nor2b2
nor3
nor3_g
nor3b1
nor3b2
nor3b3
nor4
nor4_g
nor4b1
nor4b2
nor4b3
nor4b4
nor5
nor6
nor7
nor8
nor9
norX
oand2
obuf
obuf_ann
obuf_g
obuft
obuft_g
ofd
ofde
ofdi
ofdt
ofdtx
ofdtxi
ofdx
ofdxi
omux2
onand2
onor2
oor2
opad
opad_sim
or2
or2_g
or2b1
or2b2
or3
or3_g
or3b1
or3b2
or3b3
or4
or4_g
or4b1
or4b2
or4b3
or4b4
or5
or6
or7
or8
or9
orX
oxnor2
oxor2
pulldown
pulldown_g
pullup
pullup_g
ram16x1
ram16x1d
ram16x1s
ram16x2d
ram16x2s
ram16x4d
ram16x4s
ram16x8d
ram16x8s
ram32x1
ram32x1s
ram32x2s
ram32x4s
ram32x8s
rom16x1
rom32x1
Shifter
SimulationBuffer
startup
tb_andX
tck
tdi
tdo
TESTXC4000Library
tms
upad
vcc
wand
wor2and
XC4000TechMapper
XilinxTechMapper
xnor2
xnor2_g
xnor3
xnor3_g
xnor4
xnor4_g
xnor5
xnor6
xnor7
xnor8
xnor9
xnorX
xor2
xor2_g
xor3
xor3_g
xor4
xor4_g
xor5
xor6
xor7
xor8
xor9
xorX
Xwire