cvt was developed to give users a friendly simulation and debugging environment which can be used as is. The CVT environment offers a number of tools to watch the behavior of your circuit. The most popular viewers in CVT are the Browser Tree and Port Table, the Schematic Viewer, the Waves Viewer, and the Memory Viewer. Each of these viewers has a menu bar with menu options specific to it's function. There is also a command line on the bottom of some viewers to enter commands you wish CVT to perform. The cvt tool is described in more detail in a later section of the user's manual.
The dynamic testbench (dtb) tool was used in the "Getting Started" section of the JHDL documentation. dtb provides a way of loading a circuit into cvt and simulating and netlisting it without having to write a testbench. Its capabilities are described in a later section of the user's manual.
JHDL provides a logic simulator for JHDL circuits. It is a statically scheduled simulator which results in reasonably fast simulations. The JHDL API's are set up in such a way that the simulator appears to be tightly integrated with all of cvt. The JHDL simulator is also described in a later section.
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Last updated on 11 May 2006