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Intro to Circuit Verification

In addition to providing a mechanism for the entry of designs, JHDL provides a full framework for the visualization, simulation, and verification of the resulting circuits. JHDL provides an open, API-based framework to allow for the creation of a wide variety of circuit visualization tools. Thus, all information required is provided for a user to create his own simulation and verification environment if desired. However, JHDL also provides a default simulation/debug environment called cvt which stands for Circuit Visualization Tool.

cvt was developed to give users a friendly simulation and debugging environment which can be used as is. The CVT environment offers a number of tools to watch the behavior of your circuit. The most popular viewers in CVT are the Browser Tree and Port Table, the Schematic Viewer, the Waves Viewer, and the Memory Viewer. Each of these viewers has a menu bar with menu options specific to it's function. There is also a command line on the bottom of some viewers to enter commands you wish CVT to perform. The cvt tool is described in more detail in a later section of the user's manual.

The dynamic testbench (dtb) tool was used in the "Getting Started" section of the JHDL documentation. dtb provides a way of loading a circuit into cvt and simulating and netlisting it without having to write a testbench. Its capabilities are described in a later section of the user's manual.

JHDL provides a logic simulator for JHDL circuits. It is a statically scheduled simulator which results in reasonably fast simulations. The JHDL API's are set up in such a way that the simulator appears to be tightly integrated with all of cvt. The JHDL simulator is also described in a later section.

Where To From Here?

It is recommended you read the remainder of the sections in this part of the user's manual to understand how to verify the correctness of your circuits. Start with cvt - The Circuit Visualization Tool Suite.

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